1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) and, more particularly, to a semiconductor memory having an output buffer circuit through which a large current flows.
2. Description of the Related Art
There is a demand for higher processing speed of a semiconductor integrated circuit. For example, in a semiconductor memory, a fast access time and a decrease in power consumption become important subjects.
FIG. 1 is a block diagram showing a conventional random access memory (RAM) in which an operation of an internal circuit is controlled by a pulse signal. This pulse signal is generated in synchronism with a change of an address input signal. A fast access time and a decrease in power consumption are attempted by using the pulse signal. In this case, in order to simplify a description, a circuit portion associated with data writing is omitted. Referring to FIG. 1, reference numerals 11 denote a plurality of address input terminals; 12, a column address buffer; 13, a row address buffer; 14, a column decoder; 15, a row decoder; 16, column selection lines; 17, row lines: 18, a memory cell array having a plurality of memory cells (not shown) in a matrix form to be selected by signals through row lines 17; 19, bit lines; 20, a column gate circuit; 21, a sense amplifier; 23, an output buffer circuit; 24, a data output terminal; and 25, a pulse signal generator.
Column and row address buffers 12 and 13 respectively generate internal address signals corresponding to column and row address input signals externally supplied from circuits outside the memory. Pulse signal generator 25 receives the internal address signals output from column and roW address buffers 12 and 13, and outputs a pulse signal when the logic level of at least one of the address signals is changed. The pulse signal output from pulse signal generator 25 is supplied to memory cell array 18, sense amplifier 21, and output buffer circuit 23. Operation of memory cell array 18, sense amplifier 21, and output buffer circuit 23 are controlled by this pulse signal. For example, a precharge operation of each bit line in memory cell array 18, a sensing operation of data in sense amplifier 21, and an output operation of data in output buffer circuit 23 are respectively controlled by this pulse signal. The above pulse signal is set to have a pulse wide enough to allow memory cell array 18, sense amplifier 21, and output buffer circuit 23 to be operated with a sufficient margin.
In a semiconductor memory, a large capacitance connected to a data output terminal e.g., a load capacitor of about 100 pF, must be driven by an output buffer circuit. For this reason, in the output buffer circuit, the current driving ability of a transistor on an output stage is very large so as to satisfactorily drive such a large load capacitor.
FIG. 2 shows an arrangement of the output stage of such an output buffer circuit. The output stage of the output buffer circuit is constituted by p-channel MOS transistor Qp having the source connected to positive power source voltage V.sub.DD and the drain connected to data output terminal 24, and n-channel MOS transistor Qn having the source connected to V.sub.SS (ground) and the drain connected to output terminal 24. One of transistors Qp and Qn is set in an ON state according to data detected by sense amplifier 21. Load capacitor Co connected to data output terminal 24 is charged toward V.sub.DD or discharged to V.sub.SS through the ON-state transistor. The conductances of both transistors are set to be large so as to enable outputting quickly data Dout from output terminal 24 by performing charging and discharging of capacitor Co using a large current.
Power source voltage V.sub.DD and ground voltage V.sub.SS are applied from power source unit 200 to this output buffer circuit through wiring lines 201 and 202. With this arrangement, when a large current flows through lines 201 and 202, voltages V.sub.DD and V.sub.SS greatly vary due to the influences of inductances 203 and 204 present on lines 201 and 202. More specifically, if the value of each of inductances 203 and 204 is set to be L, and a rate of change in current flowing through line 201 or 202 as a function of time is defined as di/dt, potential change .DELTA.v occurring at line 201 or 202 can be given by the following equation: EQU .DELTA.v=L.(di/dt) 1
FIG. 3 is a timing chart showing a voltage/current change at each node in the circuit shown in FIG. 2. Referring to FIG. 3, reference symbol Is denotes a drain current of p-channel MOS transistor Qp; and It, a drain current of n-channel MOS transistor Qn. When transistors Qp and Qn are switched, and drain current Is or It of transistor Qp or Qn flows, voltages V.sub.DD and V.sub.SS vary, as shown in FIG. 3.
If a large current flows through the output stage when data is output from the output buffer circuit in this manner, voltages V.sub.DD and V.sub.SS supplied to semiconductor memory vary. An operation error of the semiconductor memory is occurred by these potential changes. An operation error caused by charging and discharging currents with respect to a load capacitor tends to be more easily caused as a semiconductor memory is required to be operated at a higher speed, and charging and discharging of the load capacitor are performed for a shorter period of time.
Various operation errors are caused by such a variation in power source voltage. One of the operation errors is associated with a sense amplifier. Normally, the sense amplifier detects a very small potential change in a semiconductor memory so as to accomplish a fast access time. However, since power source voltage V.sub.DD and ground voltage V.sub.SS equivalent to those applied to the output buffer circuit are applied to the sense amplifier, an operation error of the sense amplifier is caused by variation of V.sub.DD and V.sub.SS voltages. The sense amplifier compares potentials at two input nodes connected to a pair of bit lines, and detects a binary "1" or "0". In this case, the response speeds of the potentials at the two nodes with respect to the variation in voltage V.sub.DD or V.sub.SS differ from each other due to a difference between parasitic capacitance of the two nodes. For this reason, a relationship in magnitude between the potentials at the two input nodes is temporarily inverted. As a result, erroneous data may be detected. Such an operation error tends to occur as a difference between the potentials at the two input nodes of the sense amplifier is small. In order to provide a high speed of operation, such a potential difference is preferably set to be minimum. Therefore, such an operation error tends to more easily occur in a semiconductor memory required to be operated at a high speed. In addition, variations of voltages V.sub.DD and V.sub.SS in a semiconductor memory induce an operation error of an input stage, e.g., a column or row address buffer.
Thus, the changes of the voltages V.sub.DD and V.sub.SS occur in a semiconductor memory device when data is read out from the output buffer circuit. The potential level of the data supplied to the address input section of the memory device from another semiconductor integrated circuit does not change, even if the voltage V.sub.DD or V.sub.SS of the semiconductor integrated circuit is changed. As a result, an error occurs in the semiconductor memory device.
For example, if the voltage V.sub.SS in the semiconductor memory device changes to the negative direction, while data of a logic "0" level is supplied to the address data input section, the address data input section will recognize the input data as a logic "1" data, since the potential difference between the input data and the voltage V.sub.SS becomes large.
That is, if the column or row address buffer operate erroneously, an output from the column or row address buffer is temporarily inverted by the variations in voltages V.sub.DD and V.sub.SS. As a result, pulse signal generator 25 outputs a pulse signal in the same manner as in a normal change in address input. Thus, memory cell array 18, sense amplifier 21, and output buffer circuit 23 receive this pulse signal and hence start the respective operations an the same manner as in a normal change in address input. Thereafter, undesired data is output from output buffer circuit 23, and an operation error occurs.
As described above, in the conventional semiconductor IC, the change of a power source voltage is generated when the output buffer circuit outputs a data, and an operation error tends to be caused by this change of a power source voltage.